1. Field of the Invention
The present invention relates to a semiconductor memory device, and, more particularly, to a semiconductor memory device operating in synchronization with an external clock signal.
2. Description of the Background Art
With development of memories with larger storage capacities in recent years, further miniaturization of transistors has been proceeded. As the size of a transistor decreases, it becomes inevitable to lower an operating power supply voltage (hereinafter, simply referred to as an "operating voltage") to ensure reliability of the operation of the transistor.
In order for an MOS transistor to operate with such low operating voltage without damaging its operating speed, it is necessary to lower the threshold voltage of the transistor. However, such reduction in the threshold voltage causes inadequate cutoff of the transistor at the time of shutdown, thereby leading to generation of a leakage current due to a sub-threshold current. Low-power characteristic that is one of the most significant features of the CMOS circuits is thus lost.
FIG. 13A shows a circuit configuration of a CMOS inverter circuit 500, and FIG. 13B shows a relation between the threshold voltage and the sub-threshold voltage in inverter circuit 500.
Referring to FIG. 13A, inverter circuit 500 includes a p channel transistor QP and an n channel transistor QN which are serially connected to each other between an operating voltage Vdd line and a ground voltage Vss line, and which have gates receiving an input signal Qin, respectively. These transistors QP and QN connected to each other have drains connected to each other, which becomes an output node.
Generally, the operating speed of a transistor is almost inversely proportional to the difference between the operating voltage Vdd and the threshold voltage Vt, i.e., Vdd-Vt. Therefore, Vt must be lowered in response to reduction of Vdd to ensure a sufficient operating speed of transistor. Specifically, in FIG. 13A, when input signal Qin is at Vss (an "L" level), p channel transistor QP is turned ON and n channel transistor QN is turned OFF. However, if threshold voltage Vt of n channel transistor QN is low, a sub-threshold current IL flows through transistor QN. Similarly, when input signal Qin is at Vdd (an "H" level), the sub-threshold current flows through p channel transistor QP.
Referring to FIG. 13B, the threshold voltage is defined by a gate-to-source voltage of the case where a source/drain current Ids attains a prescribed value Io. If the threshold voltage is at Vt, the source/drain current or the sub-threshold current when the gate-to-source Vgs=0V is at IL; if the threshold voltage is lowered to Vt', the sub-threshold current when Vgs=0V rises to IL'.
As explained above, by the reduction of the operating voltage of transistor in accordance with the integration to higher density, the sub-threshold current increases to a value that cannot be neglected. Further, this sub-threshold current is proportional to the transistor size (W/L, W: channel width, L: channel length). Total W/L of transistors in the entire chip increases according to the higher degree of integration of transistors, which, accompanied by the reduction of the operating voltage, further increases the leakage current generated in the entire memory.
An exemplary technique for decreasing this sub-threshold current is described in Ultra LSI Memory (written by Kiyoo Ito, Baifukan), pp. 356-366, for example.
FIG. 14 is a circuit diagram of an inverter circuit 500, shown in the above reference, for reducing the sub-threshold current by switching a source voltage.
Referring to FIG. 14, compared to inverter circuit 500 in FIG. 13A, inverter circuit 510 further includes an n channel transistor QHN between n channel transistor QN and the ground power supply voltage Vss line. N channel transistor QHN is a transistor having a threshold voltage Vvn that is higher than those of transistors QP and QN. Transistor QHN is controlled by a signal SC received at its gate. When transistor QHN is turned ON, a voltage VN or the source voltage of transistor QN becomes Vss, and normal logic operation is conducted. When transistor QHN is turned OFF, the source voltage of transistor QN is raised by Vvn. Thus, even when input signal Qin=Vss, the gate-to-source voltage Vgs of transistor QN becomes -Vvn and reverse-biased, and therefore, a sufficient OFF state can be ensured for transistor QN, and the sub-threshold current of transistor Qn can be reduced considerably.
If, instead of providing transistor QHN, a p channel transistor having a high threshold voltage is connected between transistor QP and the operating voltage Vdd line, the sub-threshold current flowing through transistor QP when input signal Qin=Vdd can be reduced to a large extent.
However, such reduction of the sub-threshold current by switching the source voltage as in inverter circuit 510 can only be successful in the case where input signal Qin has a constant value. The same effect that the sub-threshold current is reduced cannot be obtained when Qin is a random input.
In a semiconductor memory device, normally a large number of transistors, e.g., word drivers, are used in the circuits that are associated with row selection. Especially in a dynamic random access memory (hereinafter, referred to as "DRAM"), refresh operation must be conducted periodically, which operation needs dynamic row selection. Therefore, it is difficult simply to apply thereto the above-described method of reducing the sub-threshold current.
Further, with the improvement of the operating speed of a microprocessor in recent years, there has been a need to realize high-speed access of DRAM or the like employed as a main memory device. A DRAM of a synchronous type (synchronous DRAM: hereinafter, referred to as "SDRAM") has thus been used, which operates in synchronization with a clock signal.
Internal operations of such SDRAM are divided into operation in the row system and that in the column system and are controlled separately. Generally in SDRAM, a bank configuration has been employed for permitting still higher-speed operation, in which configuration a memory cell array is divided into a plurality of banks that can operate independent of one another. That is, the operation is controlled for each bank, separately for its row system operation and its column system operation.
In this type of SDRAM with such multiple bank configuration, configuration of the control circuit becomes complex, and thus, the number of circuits in the entire chip further increases. Therefore, the leakage current, or the above-described sub-threshold current, tends to increase during stand-by and in an active operation. Such increase of the leakage current is a fatal problem when the SDRAM is employed in a portable device which is battery driven, for example. Reduction of the leakage current thus becomes an essential issue.